1. Field of the Invention
The present invention relates to a semiconductor memory device incorporating redundant bit lines for replacing faulty bit lines.
2. Description of the Prior Art
Recently, the environmental cleanness in the process for manufacturing semiconductor devices has steadily been improved. Nevertheless, it is still extremely difficult for the concerned to fully prevent faulty circuits from occurring in the manufacture of semiconductor memory devices. To solve this problem, conventional semiconductor memory devices generally incorporate a redundant circuit which operates itself in place of a faulty circuit.
FIG. 1 is a block diagram of such a conventional semiconductor memory device having a redundant circuit. This conventional semiconductor memory device is adapted to replace a pair of complementary faulty bit lines 12 having malfunctioned in a test carried out during the manufacturing process with a pair of complementary redundant bit lines 22. A plurality of pairs of complementary bit lines 12 including the pair of faulty ones 12 are each connected to a pair of complementary data lines 30 via a first switch 14 controlled by a column decoder 10, whereas the pair of complementary redundant bit lines 22 is connected to the pair of data lines 30 via a second switch 24 controlled by a redundant column decoder 20.
It is to be noted that in FIG. 1 the pairs of complementary bit lines 12, redundant bit lines 22, and data lines 30 are each represented by a single line.
The pair of redundant bit lines 22 is connected to the pair of data lines 30 between the bit lines 12 and an input terminal 42 of a differential amplifier 41, as shown in FIG. 1.
Each column decoder 10 contains a fuse which is not shown specifically in the figure. According to the design applied to this conventional semiconductor memory device, when the fuse is cut off, the first switch 14 is turned OFF, whereas while the fuse remains conductive, the column decoder 10 controls an ON-OFF operation of the first switch 14 based on a column address signal received from an address bus (not shown). The fuse of the column decoder 10 connected to the faulty bit lines 12 is disconnected in a test carried out during the manufacturing process, whereas the fuse of the column decoder 10 connected to the normally operative bit lines is held conductive.
As a result, after completing the manufacturing process, the pair of faulty bit lines 12 is prohibited from being operatively connected to the data lines 30 even when the column address signal designating the faulty bit lines 12 is delivered to the column decoder 10 connected to the faulty bit lines 12. On the other hand, when the column decoder 10 connected to a pair of normally operative bit lines 12 receives the column address signal designating selection of this pair of normal bit lines 12, these normal bit lines 12 are connected to the pair of data lines 30.
The redundant column decoder 20 is designed to contain a fuse (not shown) which performs a function inverse from that provided in each of the column decoders 10. Concretely, when the fuse in the redundant column decoder 20 is cut, the redundant column decoder 20 controls an ON-OFF operation of the second switch 24 based on a column address signal received from the address bus, whereas, when the fuse remains conductive, independent of the content of the column address signal, the redundant column decoder 20 turns the second switch 24 OFF. If those bit lines 12 contain any faulty bit lines 12 in the course of an operating test during the manufacturing process, then the fuse of the redundant column decoder 20 is cut off. At the same time, a column address of the pair of faulty bit lines 12 is written in a column address detecting portion of the redundant column decoder 20, thereby the redundant column decoder 20 stores the column address of the pair of faulty bit lines 12. On the other hand, in the event that no faulty bit lines are present in those bit lines 12, then the fuse of the redundant column decoder 20 remains conductive.
After completing the manufacturing process, on receipt of a column address signal designating the faulty bit lines 12, the redundant column decoder 20 outputs a redundant signal instructing to turn the second switch 24 ON. Thereby, the second switch 24 is turned ON to allow the pair of redundant bit lines 22 to be connected to the pair of complementary data lines 30. On the other hand, on receipt of a column address signal designating a pair of normal bit lines 12, the redundant column decoder 20 outputs a non-redundant signal for turning the second switch 24 OFF. Consequently, the second switch 24 is turned OFF to disconnect the complementary redundant bit lines 22 from the pair of complementary data lines 30. If there are no faulty bit lines in those bit lines 12, then the pair of redundant bit lines 22 remains disconnected from the pair of data lines 30.
As mentioned above, the cited conventional semiconductor memory device allows the redundant bit lines 22 to be connected to the complementary data lines 30 in place of the faulty bit lines 12 based on the functional operation of those fuses provided in the column decoders 10 and the redundant column decoder 20.
The differential amplifier 41 receives data signal from a pair of normally operative bit lines 12 selected or the redundant bit lines 22 via the complementary data lines 30 before eventually amplifying the received data signal.
Recently, a significant progress has been achieved in the field of semiconductor memory devices. Those memory devices including a random access memory (RAM), a read-only memory (ROM), or the like, have respectively quadrupled the integration density every three years. And yet, in order to minimize surface area of each chip, manufacturers follow up their efforts to simplify component circuits of those semiconductor memory devices.
As a result of comprehensive study on the redundant circuits, the present inventors become aware of a fact that each column decoder 11 compulsorily contained fuses notwithstanding that all the bit lines 12 would not simultaneously malfunction, and thus resulted in the expanded surface area of each chip.